1. Field of the Invention
The present invention relates generally to systems and methods for testing silicon wafers, and more particularly for chip testing.
2. Discussion of Background Art
Currently there are two major types of silicon chip testers: logic testers and memory testers. Both types of testers include very specialized routines for performing high throughput chip testing. However, chip testing has become much more complex with the advent and popularity of modem System On a Chip (SOC) designs. SOC designs incorporate both logic and memory circuitry. Since memory testers are not capable of testing logical circuitry, manufactures have been forces to use logic testers for testing the SOCs. Unfortunately, since logic testers were never intended to test chips with large memory arrays, test routines within the logic testers have become awkwardly complex as test engineers have tried to program them to test such memory arrays. Such barriers often discourage some SOC designers and manufacturers from incorporating embedded memory, such as DRAM into their designs in order to keep costs down, even though embedding DRAM into the design would have otherwise resulted in a significantly higher chip performance.
In an attempt to address these problems, some manufacturers have added Built-In-Self-Test (BIST) circuits to their chip designs. While BIST circuits enable the chip to perform testing on itself, the silicon resources necessary to build these BIST circuits on the chip adds significant complexity to the chip and taking away silicon resources that could otherwise have been reallocated. Furthermore, most BIST circuits only generate and transmit out a pass/fail signal which by itself provides no detailed information which could enable these manufacturers to repair the chip, by such techniques as redundancy allocation, without again performing a conventional logic and/or memory array test with a logic tester as described above. Redundancy allocation is a process of repairing failed on-chip circuits using a system of redundant on-chip circuitry and fusible links.
Other BIST circuits, such as the one described in U.S. Pat. No. 6,230,290, assigned to IBM Corporation, etch a ROM and complicated BIST circuitry on the chip. The ROM contains a fixed micro-code, however, has several limitations. First the micro-code can not be modified once burned in ROM. Second, the micro-code executed test routines are rigid and un-modifiable. Third, the ROM and BIST circuitry together are almost equivalent to a second CPU/SOC design in themselves, which requires a significant customized design effort in itself, as well as significant silicon resources.
Some other BIST circuits, which fall into one of the two categories above, are described in “A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator,” by T. Yabe et al., in ISSCC digest technical paper, February 1998, pp. 72-73; “An ASIC library granulate DRAM macro with built-in self test,” by J. Dreibelbis et al., in ISSCC digest technical papers, February 1998, pp 74-75; and “An embedded DRAM Hybrid Macro with Auto Signal management and Enhanced-on-chip tester,” by N. Watanabe et al, in ISSCC digest technical papers, February, 2001, pp 388-389.
Also, since memory defects are very much foundry sensitive, none of the above described BIST algorithms can be universally applied to a large number of logic and/or memory chips, which each currently require unique, customized, and rigid conventional memory testing. Standardized BIST ROMs or circuits simply can not be designed to affect all the different test algorithms which each separate foundry requires.
Thus, well known and laborious “direct memory testing” techniques, which use a large numbers of pads and associated complex pad multiplexing functions, have largely remained as the only way to perform embedded memory testing, especially for embedded DRAM. Such testing is however, very costly in terms of testing time and capital equipment expense.
In response to the concerns discussed above, what is needed is a system and method for chip testing that overcomes the problems of the prior art.